InnoPhase IoT
RFIC Design Engineer (New Graduate)
About this role
InnoPhase IoT seeks a new graduate RFIC design engineer to develop RF, analog, and mixed-signal circuits for wireless semiconductor products in advanced CMOS technologies. The role involves circuit design, simulation, layout collaboration, and silicon validation in a dynamic small company environment focused on innovation and growth.
What you'll do
- Design and simulate RF front-end and analog circuits including LNAs, PAs, mixers, oscillators, and filters at transistor level
- Perform circuit simulations and behavioral modeling using Cadence, Matlab, and related EDA tools
- Conduct EM simulation, passive component modeling, and post-layout verification analysis
- Support silicon bring-up, lab testing, and performance characterization using RF equipment
- Collaborate with layout, digital, firmware, and test teams on system integration and production testing
- Document designs and communicate technical results to engineering teams
What they're looking for
- RFIC and mixed-signal circuit design
- RF CMOS fundamentals and analog circuit principles
- Cadence Virtuoso, Spectre, and EM simulators
- Python and C++ programming
- IC layout and post-layout verification concepts
- RF measurement equipment operation
- Problem-solving and debugging
- Cross-functional team collaboration
Benefits
- Work with brilliant engineers on cutting-edge wireless technology
- Diverse learning opportunities across multiple engineering disciplines
- Access to RF lab equipment and hands-on silicon validation
- Culture emphasizing employee growth, recognition, and meaningful contributions
- Located in San Diego, California
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InnoPhase IoT
InnoPhase IoT develops RF and analog semiconductor products for wireless IoT applications. The company is hiring circuit design engineers and release/integration engineers to work on wireless chip design, firmware releases, and embedded software deployment.
- Website
- innophase.com
Likely interview questions
- Walk us through a specific RF circuit you designed or analyzed in your graduate research—what were the key performance metrics you optimized for, and what simulation tools did you use?
- Describe your experience with Cadence Virtuoso and Spectre. Have you performed post-layout simulation or parasitic extraction, and how did layout effects impact your circuit performance?