IMC
Hardware Engineer
About this role
IMC's Global Hardware team is hiring a Hardware Engineer in Chicago to design and develop custom ASICs for high-performance trading infrastructure. You'll work across the full ASIC lifecycle—from RTL design through verification and deployment—collaborating with software engineers and researchers to solve latency-critical technical challenges.
What you'll do
- Design and implement RTL for next-generation ASIC platforms using SystemVerilog
- Develop and execute verification strategies, unit tests, and validation environments for hardware components
- Contribute to architecture discussions and translate requirements into scalable hardware solutions
- Debug design and integration issues throughout the ASIC development process
- Develop scripts and tooling to improve engineering workflows and automation
- Ensure designs meet reliability, performance, and maintainability requirements
What they're looking for
- RTL design with SystemVerilog
- Digital design fundamentals
- Verification and testing methodologies
- Multi-clock-domain design and clock-domain crossing
- Ethernet protocols and networking fundamentals
- C++ and scripting languages (Python, Bash)
- Problem-solving and debugging
- Cross-disciplinary collaboration
Benefits
- Work on high-impact engineering challenges in latency-sensitive trading systems
- Broad ownership with exposure to multiple aspects of the design process
- Collaborative team culture with minimal specialization constraints
- Discretionary bonus eligibility
- Comprehensive benefits package
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IMC
IMC builds trading technology and financial systems powered by software, machine learning, and hardware engineering. The company is hiring interns and graduate-level engineers and researchers across software, machine learning, and hardware disciplines to develop trading algorithms, research strategies, and collaborative technology solutions.
View all jobs at IMCLikely interview questions
- Walk us through your experience with RTL design in SystemVerilog. Can you describe a specific ASIC or hardware project where you wrote RTL and what challenges you faced?
- How do you approach verification and testing for RTL designs? Tell us about a time when you caught a critical bug in hardware verification and how you debugged it.