Etched
Physical Design Engineer
About this role
Etched seeks an experienced Physical Design Engineer to lead block-level chip implementation and optimization for AI inference hardware. You'll own timing closure, PPA optimization, manage third-party design work, and enhance design flows for a fast-growing frontier AI company.
What you'll do
- Own block-level physical design implementation and verification through GDSII sign-off
- Drive timing closure and PPA optimization on advanced process nodes
- Collaborate with RTL designers to provide physical design feedback and improvements
- Supervise and manage outsourced physical design work to third-party vendors
- Optimize EDA tool flows and automate physical design processes
- Create dashboards and metrics tracking physical design project convergence
What they're looking for
- Physical design flow (RTL synthesis to GDSII)
- Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) tools
- Advanced node timing closure (5nm and below)
- Sign-off tools (PrimeTime, Tempus, Voltus)
- UPF low-power design, power verification, and scan insertion
- Floorplanning, placement, routing, and IR/EM analysis
- Python or scripting languages
- ML/LLM architecture familiarity
Benefits
- Medical, dental, and vision coverage with generous premiums ($500/month credit option)
- Wellness benefits including fitness and mental health programs
- Daily lunch and dinner provided in office
- Unlimited compute budget subject to ROI justification
- Collaborative engineering culture with research integration
- Hybrid arrangement: ~2 weeks/month in San Jose first quarter, then ~1 week/month
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your experience closing timing on advanced process nodes (5nm and below). What were the biggest challenges you faced and how did you overcome them?
- Describe your hands-on experience with Cadence Innovus or Synopsys ICC2. How have you optimized PPA in an RTL-to-GDSII flow?