Etched
Design Verification Engineer - SoC
About this role
Etched seeks a Design Verification Engineer to validate custom chip IPs (systolic arrays, DMA engines, NoCs) for AI inference hardware. You'll collaborate across architects, RTL designers, and software teams to ensure performance correctness from pre-silicon modeling through post-silicon tuning.
What you'll do
- Develop test plans and infrastructure for performance verification, correlation, and tuning across pre- and post-silicon stages
- Create SystemVerilog and Python tests to validate RTL against performance models and debug discrepancies
- Build and maintain architectural performance models for chip subsystems
- Design SystemVerilog checkers and coverage monitors to verify performance features
- Debug performance bottlenecks and conduct silicon-level tuning with software/firmware teams
- Drive end-to-end performance optimization ensuring hardware utilization and software efficiency
What they're looking for
- Digital design and RTL/ASIC design flows
- SystemVerilog testbench and checker development
- Python scripting for automation and data analysis
- Performance modeling and simulation
- Memory hierarchies, pipelines, interconnects, and accelerators
- Performance profiling tools and kernel-level metrics
- Compiler optimizations and workload tuning
- Coverage analysis and monitoring
Benefits
- Medical, dental, and vision coverage with $500/month credit option
- Wellness programs including fitness and mental health
- Daily lunch and dinner provided
- Unlimited compute budget subject to ROI justification
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your experience with SystemVerilog testbenches and checkers. How have you approached verifying performance features in RTL designs?
- Describe a time you built or maintained a performance model for a chip subsystem. How did you correlate it with actual silicon results?