Etched
Design Verification Engineer - Internal IP
About this role
Etched seeks a Design Verification Engineer to validate custom high-performance IPs (systolic arrays, DMA engines, NoCs) for AI inference chips. You'll develop UVM testbenches, debug complex RTL issues, and collaborate across architecture, design, software, and emulation teams to ensure silicon-ready verification.
What you'll do
- Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMAs, NoCs, and memory subsystems
- Define and execute verification plans covering functional correctness, corner cases, and performance bottlenecks
- Debug complex datapath and protocol issues in RTL and testbench environments
- Collaborate with architects and designers to validate functionality and design intent
- Partner with SW, FW, and emulation teams on end-to-end bring-up and debug
- Build reusable DV infrastructure, coverage models, and methodology improvements
What they're looking for
- UVM and SystemVerilog
- Digital design debugging and problem-solving
- Computer architecture and digital design fundamentals
- Datapath, memory system, and interconnect verification
- SystemVerilog Assertions (SVA) and formal verification
- Scripting (Python, Perl, TCL)
- High-throughput fabric verification
- AXI/NoC protocol experience
Benefits
- Medical, dental, and vision coverage with generous premiums ($500/month credit for waiving)
- Wellness benefits including fitness and mental health
- Daily lunch and dinner in office
- Unlimited compute budget subject to ROI justification
- Fully in-person team environment in San Jose
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your experience developing UVM testbenches for high-performance IPs. What was the most complex verification challenge you've tackled, and how did you approach it?
- Describe your experience verifying datapaths, memory systems, or interconnects. How do you ensure coverage of corner cases and concurrent scenarios?