Etched
Design Verification Engineer - Interface IP
About this role
Etched seeks a Design Verification Engineer to own verification of Interface IP subsystems (PCIe, Ethernet, CPU, peripherals) for AI inference hardware. You'll develop UVM-based testbenches, validate vendor IP integration, and drive coverage closure across complex hardware-software interactions.
What you'll do
- Own end-to-end verification of IP subsystems including PCIe, Ethernet, CPU architectures, and low-power peripherals
- Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance validation
- Manage vendor IP configurations and coordinate with internal teams on IP handoff and integration
- Collaborate with SoC and integration DV teams to validate IP interaction within the broader chip architecture
- Drive coverage closure by defining metrics, analyzing gaps, and testing corner cases and stress scenarios
- Validate seamless hardware-software stack interaction across prefill and decode workloads
What they're looking for
- Design verification (5+ years)
- SystemVerilog and UVM
- PCIe, Ethernet, AXI/AMBA, ARM/ARC CPU protocols
- Testbench development and reusable verification methodologies
- Vendor IP integration and third-party VIP handling
- Cross-functional collaboration with RTL, software, and emulation teams
- Coverage analysis and sign-off
- Corner-case bug detection and creative problem-solving
Benefits
- Medical, dental, and vision coverage with $500/month credit for waiving medical
- Wellness benefits including fitness and mental health
- Daily lunch and dinner in office
- Unlimited compute budget subject to ROI justification
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your experience developing UVM/SystemVerilog verification environments. Can you describe a complex testbench you built and how you structured it for reusability and scalability?
- Tell us about a time you owned verification for an interface IP (PCIe, Ethernet, AXI, or similar). How did you approach coverage closure and what corner cases did you uncover?