Astera Labs
Physical Design/CAD Engineer
About this role
Astera Labs seeks a Physical Design/CAD Engineer to lead RTL-to-GDS ownership for connectivity ASIC designs, managing synthesis, place-and-route, timing, and signoff across complex chips for major cloud and networking customers. The role combines EDA flow development, physical design execution, and cross-functional collaboration to achieve optimal performance, power, and area in advanced semiconductor nodes.
What you'll do
- Support and build EDA tool flows for physical design across synthesis, place-and-route, extraction, and signoff stages
- Drive physical design activities ensuring robust signoff for complex SoCs and subsystems
- Architect flow improvements and enhance backend design methodology for high-performance results
- Define requirements with cross-functional teams to achieve best power, performance, and area (PPA)
- Own block-level partitions through closure including place-and-route, timing analysis, and design rule checks
- Partner with design, implementation, and verification teams to drive convergence and provide signoff expertise
What they're looking for
- Place-and-route (PnR) and full-chip timing closure
- Cadence and/or Synopsys EDA tool proficiency
- Advanced node design (7nm or below)
- Scripting in Tcl, Python, or Perl
- Extraction, formal verification, and DRC/LVS expertise
- Physical design flow development and methodology
- Cross-functional collaboration and independent problem-solving
- High-speed digital design concepts
Benefits
- Competitive base salary range: $135K–$165K (Senior) or $160K–$195K (Staff)
- Opportunity to work on AI infrastructure for leading hyperscalers
- Fully on-site role in San Jose with established technical teams
- Potential ownership of design blocks from implementation through signoff
- Professional development in cutting-edge semiconductor connectivity technologies
- Inclusive workplace culture welcoming diverse backgrounds and experiences
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Astera Labs
Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.
View all jobs at Astera LabsLikely interview questions
- Walk us through your experience with PnR and timing closure flows on advanced nodes (7nm or below). What were the biggest challenges you faced and how did you overcome them?
- Describe your approach to architecting and improving physical design flows. Can you give an example of a flow enhancement you've implemented that improved PPA?