Anduril Industries
FPGA DSP Engineer
About this role
Anduril Industries seeks a Senior FPGA DSP Engineer to lead digital signal processing and FPGA design for advanced airborne radar systems. You will translate algorithmic requirements into high-performance implementations, establish design standards, and mentor engineers while working with Xilinx platforms on cutting-edge defense technology.
What you'll do
- Lead FPGA architecture, design, and verification for airborne radar systems from concept through production
- Convert signal processing algorithms into optimized FPGA implementations on Xilinx SOC/FPGA platforms
- Establish design processes, coding standards, and verification methodologies for the team
- Design and implement digital signal processing chains including data acquisition, filtering, and real-time processing
- Perform timing analysis, resource optimization, and debugging of complex FPGA designs
- Mentor engineers and maintain design documentation including specifications and verification plans
What they're looking for
- SystemVerilog/VHDL RTL design
- Xilinx FPGA tools (Vivado, Quartus)
- Digital signal processing implementation
- FPGA verification and simulation
- Radar system architecture
- Timing analysis and resource optimization
- Technical leadership and project management
- Design documentation and specifications
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Anduril Industries
Anduril Industries builds autonomous defense systems including underwater vehicles, unmanned aircraft, and electronic warfare platforms for the Department of Defense. The company is hiring across mechanical engineering, mission operations, software development, technical leadership, and advanced manufacturing roles to support the design, deployment, and production of these mission-critical systems.
- Website
- anduril.com
Likely interview questions
- Walk us through a complex DSP algorithm you've implemented on an FPGA—how did you translate the algorithmic requirements into RTL, and what were your timing/resource optimization challenges?
- Describe your experience with Xilinx Vivado and SOC/FPGA platforms. How have you approached design verification and timing closure on production radar or signal processing systems?